13.3‑inch E‑Paper Module – High Contrast E Ink Display

Product Details: JicTech 13.3‑Inch E‑Paper Display Module

Visión general

The JS1330DNG05‑TNG‑A0 is a large‑format Active Matrix Electrophoretic Display (AM EPD) module designed for high‑visibility, low‑power information display applications. With a 13.3‑inch diagonal active area, it offers a clear, stable image with support for three colors (black, white, red) without the need for a backlight. The module integrates a complete driver system including gate/source buffers, timing controller, DC‑DC converters, SRAM, LUT, and VCOM generation, making it easy to interface via SPI. Its pure reflective, bi‑stable nature ensures content remains visible with zero power between updates.

Características principales

Large, High‑Resolution Display: 13.3‑inch active area with 960×680 pixels for detailed text and graphics.
Three‑Color Support: Black, White, and Red (BWR) for enhanced visual communication.
Ultra‑Low Power Consumption: Deep sleep current as low as 3 µA; power only required during updates.
Integrated Driver System: On‑chip SSD1677 controller with OTP waveform storage, temperature sensor interface, and internal voltage regulators.
Dual Interface Options: Configurable 4‑wire SPI or 3‑wire SPI via hardware selection pin (BS).
Wide Viewing Angle & High Contrast: Pure reflective mode with excellent readability from all angles.
Robust & Slim Design: Module thickness of only 1.20 mm, RoHS compliant, and tested for industrial reliability.
Long Operational Life: Supports up to 1,000,000 update cycles or 5 years of continuous use.

Aplicaciones

Electronic Shelf Labels (ESL) and retail price tags
Digital signage and information boards
Public transport timetables and wayfinding
Industrial and warehouse labeling
Smart office conference room displays

Especificaciones técnicas

Categoría	Parámetro	Especificación	Unidad	Condiciones / Notas
General	Nombre del modelo	JS1330DNG05‑TNG‑A0	–	–
	Tipo de pantalla	Active Matrix Electrophoretic Display (AM EPD)	–	BWR (Black‑White‑Red)
	Tamaño de la pantalla	13.3	En pulgadas	–
	Resolución	960 (H) × 680 (V)	Píxeles	–
	Área activa	275.52 × 195.16	mm	–
	Paso de píxeles	0.287 × 0.287	mm	Rectangle
	Esquema Dimensiones	286.32 (H) × 212.26 (V) × 1.20 (D)	mm	–
	Peso	106.7 ± 0.5	g	–
Eléctrico	Tensión de alimentación lógica (VDD)	2.2 – 3.7 (Typ. 3.0)	V	–
	High‑Level Input Voltage (VIH)	0.8 × VDD	V	–
	Low‑Level Input Voltage (VIL)	0.2 × VDD	V	–
	Typical Operating Current	Typ. 20	mA	During update @ VDD=3.0V
	Deep Sleep Current	Typ. 3, Max. 5	µA	DC/DC off, no clock, RAM not retained
	Image Update Time	Typ. 25	sec	@ 23°C
Driver IC & Voltages	Conductor IC	SSD1677	–	–
	Positive Source Voltage (VSH)	+14.5 to +15.5 (Typ. +15)	V	–
	Negative Source Voltage (VSL)	‑15.5 to ‑14.5 (Typ. ‑15)	V	–
	Positive Gate Voltage (VGH)	+21 to +23 (Typ. +22)	V	–
	Negative Gate Voltage (VGL)	‑21 to ‑19 (Typ. ‑20)	V	–
	VCOM Voltage	To be defined (TBD)	V	–
Óptico	White Reflectivity	Min. 30, Typ. 35	%	Measured with Eye‑One Pro
	Relación de contraste	Min. 8:1	–	Indoor conditions
	Update Time	Typ. 25	sec	Full refresh @ 23°C
Interfaz	Communication Interface	4‑wire SPI (BS=L) or 3‑wire SPI (BS=H)	–	Configurable via BS pin
	Temperature Sensor Interface	I²C (TSCL, TSDA)	–	Supports external sensor
	Busy Indicator	BUSYN pin	–	Active low during operations
Medio ambiente	Temperatura de funcionamiento	10 to +40	°C	–
	Temperatura de almacenamiento	‑25 to +40	°C	–
	Operating Life	1,000,000 updates or 5 years	–	–

Pin Assignment (24‑pin connector)

Pin	Nombre	I/O	Descripción	Pin	Nombre	I/O	Descripción
1	NC	–	Do not connect	13	SCL	I	Serial clock (SPI)
2	GDR	O	MOSFET gate drive control	14	SDA	I	Serial data (SPI)
3	RESE	I	Current sense input	15	VDD	P	Interface logic power
4	NC	–	Do not connect	16	VDD	P	Chip power supply
5	VDHR	C	Positive source voltage 1	17	VSS	P	Suelo
6	TSCL	O	I²C clock for temp sensor	18	VDDD	C	Core logic power
7	TSDA	I/O	I²C data for temp sensor	19	VPP	P	OTP programming supply
8	BS	I	Bus interface selection (L=4‑wire, H=3‑wire)	20	VSH	C	Positive source voltage 2
9	BUSYN	O	Busy output (active low)	21	VGH	C	Positive gate voltage
10	RSTN	I	Reset (active low)	22	VSL	C	Negative gate voltage
11	D/C	I	Data/command control	23	VGL	C	Negative source voltage
12	CSB	I	Chip select (active low)	24	VCOM	C	VCOM driving voltage

Interface Timing (SPI)

Parámetro	Write Mode	Read Mode	Unidad
SCL Clock Frequency (max)	20	2.5	MHz
CS# Setup Time before SCL rising edge	20	100	ns
CS# Hold Time after SCL falling edge	20	50	ns
CS# High Time between transfers	100	250	ns
SCL High Time	25	180	ns
SCL Low Time	25	180	ns

Command Set Highlights

Driver Output Control (0x01): Gate settings and MUX configuration.
Deep Sleep Mode (0x10): Reduces power to microamps.
Temperature Sensor Control (0x18): Select internal or external sensor.
Write RAM (BW: 0x24, RED: 0x26): Load image data into display memory.
Master Activation (0x20): Trigger display update sequence.
Border Waveform Control (0x3C): Configure border display behavior.

Reliability & Environmental Testing

Low‑Temperature Storage: ‑25°C for 240 hours
High‑Temperature Storage: 60°C, 40% RH for 240 hours
Ciclos de temperatura: ‑25°C ↔ +60°C, 50 cycles
High‑Humidity Operation: 40°C, 80% RH for 240 hours
ESD Protection: Air discharge ±15 kV; contact discharge ±8 kV (finished product)
UV Exposure Resistance: 765 W/m² for 168 hours at 40°C

Normas de calidad e inspección

Inspection Level: Level II (GB/T 2828.1‑2012)
AQL: Major defects 0.65, Minor defects 1.5
Viewing Conditions: 30 cm distance, ±45° angle, 700‑1000 lux ambient
Zone Definitions: A‑zone (active area), B‑zone (outside active area) with specific defect allowances for dots, lines, and cosmetic issues.

Notas sobre manipulación y seguridad

Handle with care; display glass is fragile and may break if dropped.
Avoid exposure to harmful gases, moisture, and extreme temperatures.
Do not stack modules or apply pressure to the active area.
Clean only with a soft, dry cloth; avoid chemicals.
Store in original packaging at 15‑35°C, 30‑60% RH, away from direct sunlight.

El paquete incluye

13.3‑inch E‑Paper display module (JS1330DNG05‑TNG‑A0)
24‑pin connector interface
Reference design schematic for SPI interface (typical application circuit)

Información para pedidos

Model: JS1330DNG05‑TNG‑A0
Version: V0.1 (Preliminary Specification)
Driver IC: SSD1677
Interface: 24‑pin FPC
RoHS compliant

Note: Specifications are based on preliminary datasheet V0.1 and are subject to change. For design‑in support, custom configurations, or reliability requirements, please contact JicTech technical sales.